1. Field of the Invention
The present invention relates to a liquid crystal display (LCD) device, and more particularly, to a gate-in-panel (GIP) type liquid crystal display (LCD) device and a method of manufacturing the same.
2. Discussion of the Related Art
With the rapid development in information technology, flat panel display (FPD) devices, which have the properties of a thin profile, low weight and low power consumption, have been developed. Among the FPD devices, liquid crystal display (LCD) devices are widely used for notebook computers and desktop monitors because of their excellent characteristics of resolution, color display and display quality.
In general, a liquid crystal display (LCD) device includes two substrates, which are spaced apart and face each other, and a liquid crystal layer interposed between the two substrates. Each of the substrates includes an electrode, and the electrodes of each substrate also face each other. A voltage is applied to each electrode, and an electric field is induced between the electrodes. Liquid crystal molecules of the liquid crystal layer are rearranged by varying the intensity of the electric field, and the transmittance of light is changed according to the arrangement of the liquid crystal molecules, thereby displaying images.
The LCD device includes a liquid crystal panel including two substrate and a liquid crystal layer interposed therebetween, a backlight unit disposed under the liquid crystal panel and functioning as a light source, and a driving circuit unit disposed at an outer portion of the liquid crystal panel and driving the liquid crystal panel.
Generally, the driving circuit unit includes a printed circuit board (PCB). The driving circuit unit is classified into a gate driving circuit unit, which is connected to gate lines of the liquid crystal panel and provides gate signals to the gate lines, and a data driving circuit unit, which is connected to data lines of the liquid crystal panel and provides data signals to the data lines. The driving circuit unit may be attached to one side or two sides of the liquid crystal panel by a tape carrier package (TCP) method.
However, the size and weight of the LCD device increases if the gate driving circuit unit and the data driving circuit unit are separately attached. Accordingly, a gate-in-panel (GIP) type LCD device has been suggested, in which some circuits of the gate driving circuit unit are formed simultaneously with switching elements of the liquid crystal panel, and the other circuits of the gate driving circuit unit are combined into the data driving circuit unit and attached to a side of the liquid crystal panel.
FIG. 1 is a plan view of a GIP type LCD device according to the related art. In FIG. 1, the GIP type LCD device 10 includes a first substrate 20, a second substrate 50 over the first substrate 10, and a liquid crystal layer (not shown) interposed between the substrates 20 and 50. The first substrate 20, which may be referred to as an array substrate, includes a display area DA for displaying images and a non-display area NDA for driving circuits and signal lines.
In the display area DA of the first substrate 20, gate lines 22, data lines 24, thin film transistors Tr and pixel electrodes 45 are formed. The gate lines 22 and the data lines 24 cross each other to define pixel regions P. The thin film transistors Tr are connected to the gate lines 22 and the data lines 24, and the pixel electrodes 45 are connected to the thin film transistors Tr, respectively.
In the non-display area NDA of the first substrate 20, gate pads 42, data pads 44, gate circuit blocks 30, gate link lines 46, data link lines 48 and connection lines 32 are formed. The data pads 44 are formed at one ends of the data link lines 48, which extend from the data lines 24 in the display area DA, and are connected to a driving circuit unit (not shown) of the outside. The gate pads 42 are formed at one ends of the gate link lines 46 and are connected to the driving circuit unit (not shown) of the outside. The gate link lines 46 are connected to the connection lines 32 through connection patterns 34. The connection lines 32 are connected to the gate circuit blocks 30, and the gate circuit blocks 30 are connected to one ends of the gate lines 22 in the display area DA.
In the LCD device 10, the driving circuit unit of the outside provides gate control signals and data signals to the gate pads 42 and the data pads 44. The gate control signals include a start signal VST, clock signals CLK1, CLK2, CLK3 and CLK4, a source voltage signal VDD, a ground voltage signal VSS, a first source voltage signal VDD1, a second source voltage signal VDD2, and a reset signal RESET. The data signals include image signals corresponding to the pixel regions P.
The gate circuit blocks 30 include shift registers. The gate circuit blocks 30 receive the gate control signals through the connection lines 32 from the driving circuit unit. The gate circuit blocks 30 generate gate signals, which turn on the thin film transistors Tr, in order and provide the gate signals to the gate lines 22.
The first and second substrates 20 and 50 are attached using a seal pattern 80. The seal pattern 80 is formed in an edge portion of the non-display area NDA. That is, the seal pattern 80 corresponds to an edge portion of the second substrate 50 and is formed in an outer portion of the gate link lines 46 right and left and in an outer portion of the display area DA up and down in the context of the figure.
A width W of the seal pattern 80 is about 1.2 mm, and a distance from the seal pattern 80 to the gate circuit blocks 30 is about 2 mm. Since an area for the seal pattern 80 is not used to display the images and is not an area for circuits, the area for the seal pattern 80 is blocked by a frame after manufacturing the LCD device. The area may be referred to as a bezel. The bezel increases the non-display area of the LCD device and thus decreases the display area of the LCD device.
If the seal pattern 80 is formed over a portion where the gate link lines 46 and the connection lines 32 are connected to each other, the gate link lines 46 and the connection lines 32 may form a parasitic capacitor with the seal pattern 80 as a dielectric material, and this may cause delay of gate signals transmitted by the gate link lines 46 and the connection lines 32.
FIG. 2 is a view of delay of gate signals of a GIP type LCD device according to the related art, and FIG. 3 is a view showing misoperation of a gate signal of a GIP type LCD device according to the related art. Here, the seal pattern 80 of FIG. 1 is formed over the gate link lines 46 of FIG. 1 transmitting clock signals. Referring to FIG. 2, in the GIP type LCD device according to the related art, the clock signals are distorted by resistance-capacitance delay due to a parasitic capacitance, and the gate circuit blocks 30 of FIG. 1 generate gate signals from the distorted clock signals. Accordingly, rising time and falling time of normal gate signals G1 are delayed, and distorted gate signals G2 are provided to the gate lines 22 of FIG. 1 to deteriorate image qualities.
Additionally, in FIG. 3, the gate circuit blocks 30 of FIG. 1 generate the gate signal using the distorted clock signals, and there may be misoperation that a gate high voltage is not normally generated. The gate control signals transmitted by the gate link lines 46 of FIG. 1 include direct current (DC) signals and alternating current (AC) signals, and the signals have different shapes in voltage values and periods. The gate control signals having various shapes cause different delay results even if the parasitic capacitances are the same. In addition, there are variations of signal distortions due to the parasitic capacitances according to positions of the gate link lines 46. As a result, misoperation may occur when the gate high voltage is generated.
Therefore, in the GIP type LCD device according to the related art, the seal pattern is formed at the outer portion of the gate link lines. Since the seal pattern area, which is not needed to display images, is added, an external grade of the LCD device is lowered, and the display area is decreased.